Difference between revisions of "CPU Clocks"

From WikiPrizm
Jump to navigationJump to search
m
Line 1: Line 1:
The processor used by the [[Casio Prizm]], thought to be a SuperH 4-A with no FPU, utilizes four clocks to regulate commands. These clocks are known as the CPU clock, the data bus clock, the SH clock and the peripheral clock.
+
The SH7724 processor used by the [[Casio Prizm]], a SuperH 4-A with no FPU, utilizes four clocks to regulate commands. These clocks are known as the CPU clock, the data bus clock, the SH clock and the peripheral clock.
  
 
==CPU clock==
 
==CPU clock==
  
The CPU clock is the main clock used by the processor. It directly controls the speed of the processor. The CPU clock itself is controlled by a clock pulse generator (CPG). The CPG consists of a input clock signal from a Crystal oscillator which is divided to achieve the standard 58 MHz clock frequency (though some claim a possibility of 27 MHz) of the Prizm. The circuit also contains two internal phase locked loops (PLL circuits) which output data about the state of the CPG.
+
The CPU clock is the main clock used by the processor. It directly controls the speed of the processor. The CPU clock itself is controlled by a clock pulse generator (CPG). The CPG consists of a input clock signal from a Crystal oscillator which is divided to achieve the standard 58 MHz clock frequency of the Prizm. The circuit also contains two internal phase locked loops (PLL circuits) which output data about the state of the CPG.
  
 
==Peripheral clock==
 
==Peripheral clock==
Line 19: Line 19:
 
==Registers==
 
==Registers==
  
There are four registers used to modify the CPG. These are the Frequency Control Register (FRQCR), the WatchDog timer Control Register (WDTCR), and Standby Control Registers 1 and 2 (STBCR & STBCR2)The exact model and family of the chip is crucial in pinpointing the addresses for such  registers, but since the Prizm is assumed to run on a SH4-A 7730, the following struct breakdown of the FRQCR shows the inferred address and layout:
+
There is one register used to modify the CPG. This is the Frequency Control Register (FRQCR), a longword memory-mapped to 0xA4150000, which can only be accessed as a longword for Read and Write operationsA description of it in technical bit-field breakdown is below:
  
  struct st_FRQCR {
+
/*  
  unsigned int PLL_VCO_selection : 2; /* [31:30] R/W */
+
* FRQCR
  /*
+
* 31: Kick
  0b11 = low speed mode
+
*   Writing 1 here updates CPG settings
  0b00 = high speed mode (over or at 150MHz)
+
* 29-24: PLL
  ALL OTHER VALUES RESTRICTED
+
*   Multiplier = (PLL + 1) * 2
  */
+
* 23-20: I_CLK
  unsigned int : 1; /* [29] R */
+
*   CPU Clock Divisor
  /*
+
* 15-12: SH_CLK
  reserved, always write with 0b0
+
*   SuperHighway Clock Divisor
  */
+
* 11-8: B_CLK
  unsigned int PLL_circuit_multiplication_ration : 5; /* [28:24] R/W */
+
*   Bus Clock Divisor
  /*
+
* 3-0: P_CLK
  0b00001: ×2
+
*   Peripheral Clock Divisor
  0b00010: ×3
+
*  
  0b00011: ×4
+
* Divisor values:  
  0b00101: ×6
+
*   0000 x1/2
  0b00111: ×8
+
*   0001 x1/3
  0b01111: ×16
+
*  0010 x1/4  
  ALL OTHER VALUES RESTRICTED
+
*  0011 x1/6  
  */
+
*  0100 x1/8  
  unsigned int CPU_clock_division_ratio : 4; /* [23:20] R/W */
+
*  0101 x1/12  
  /*
+
*  0110 x1/16  
  0b0000: ×1/1
+
*  1000 x1/24
  0b0010: ×1/2
+
*   1001 x1/32
  0b0101: ×1/4
+
*   1010 x1/36
  0b0111: ×1/6
+
*   1011 x1/48
  0b1000: ×1/8  
+
*   1101 x1/72
  0b1001: ×1/10
+
*  
  0b1010: ×1/12
+
* Updates to the FRQCR do not go into effect until 1 is written to the kick bit.
  0b1011: ×1/16
+
*---------------------------------------------------------------------------------
  0b1100: ×1/20
+
*  
  ALL OTHER VALUES RESTRICTED
+
* Before using the watchdog timer it migt be necessary to call enable_mtspcr(0, 13),
  */
+
* this will enable the RCLK signal to the WDT.
  unsigned int : 4 /* [19:16] R */
+
*/  
  /*
 
  reserved, always write with 0b0000
 
  */
 
  unsigned int SH_clock_division_ratio : 4; /* [15:12] R/W */
 
  /*
 
  0b0000: ×1/1
 
  0b0010: ×1/2
 
  0b0101: ×1/4  
 
  0b0111: ×1/6  
 
  0b1000: ×1/8  
 
  0b1001: ×1/10
 
    0b1010: ×1/12  
 
  0b1011: ×1/16  
 
  0b1100: ×1/20
 
  ALL OTHER VALUES RESTRICTED
 
  */
 
  unsigned int bus_clock_division_ratio : 4; /* [11:8] R/W */
 
  /*
 
  0b0000: ×1/1
 
  0b0010: ×1/2
 
  0b0101: ×1/4
 
  0b0111: ×1/6
 
      0b1000: ×1/8
 
  0b1001: ×1/10
 
  0b1010: ×1/12
 
  0b1011: ×1/16
 
  0b1100: ×1/20
 
  ALL OTHER VALUES RESTRICTED
 
  */
 
  unsigned int : 4 /* [7:4] R */
 
  /*
 
  reserved, always write with 0b0000
 
  */
 
  unsigned int peripheral_clock_division_ratio : 4; /* [3:0] R/W */
 
  /*
 
  0b0000: ×1/1
 
  0b0010: ×1/2
 
  0b0101: ×1/4
 
  0b0111: ×1/6
 
  0b1000: ×1/8
 
  0b1001: ×1/10
 
  0b1010: ×1/12
 
  0b1011: ×1/16
 
  0b1100: ×1/20
 
  ALL OTHER VALUES RESTRICTED
 
  */
 
  }
 
 
 
  st_FRQCR*FRQCR = (st_FRQCR*)0xA4150000;
 
  
 
==Changing clock frequencies==
 
==Changing clock frequencies==
  
One feature of the SuperH 3 processor is its ability to change operating speed. This is accomplished by writing data to the FRQCR. The FRQCR is a longword register within the CPG control unit responsible for multiplying the frequency of the base clock signal and controlling the frequency ratios of the CPU and peripheral clocks. Each of these attributes is given 4 to 5 bits within the register.
+
The one circuit that needs to be changed to make a difference in clock speed is the PLL circuit. The Prizm runs at 32x frequency, which is 58MHz (the base frequency is ~1.8MHz).  It can be overclocked to at most 87MHz.  One can simply write a new longword with the new PLL multiplication value to the FRQCR, and then rewrite it again with the top bit [31] (the FRQCR Kick, which needs to be set to 1 to "kick" the new value into place) set to change the frequencies. Valid PLL multiplication ratios are:
 +
 
 +
0b000101:×12
 +
0b000111:×16
 +
0b001011:×24
 +
0b001110:×30
 +
0b001111:×32
 +
0b010001:×36
 +
0b010111:×48
  
 
==Example code==
 
==Example code==
  
According to a manufacturer of the SuperH processor, Renesas, clock frequencies can be changed with the following C code (if the Prizm does indeed have a SH3):
+
The below will overclock the PLL circuit to 48x, effectively changing the frequency to 87MHz.
  
{| class="wikitable" style="text-align: left;" border="1"
+
void PLL_48x(void) {
 +
    unsigned int*FRQCR = (unsigned int*) 0xA4150000;
 +
    *FRQCR = *FRQCR | (0b010111 << 24) & (0b010111 << 24);
 +
    *FRQCR = *FRQCR | (0b1 << 31);
 +
}
  
|+ Changing clock frequencies
+
To reset the frequency to normal speed:
|-
 
! scope="col" |
 
  /* Clock Pulse Generater sample program
 
  Mode = 2
 
  X'tal = 16.7MHz
 
  PLL1 = *4
 
  FRQCR H'0102(startup)
 
    I:B:P=4:4:1
 
  */
 
 
 
  #include "iodefine.h"
 
  void pll4(void) ;
 
  void pll3(void) ;
 
  void idiv3(void) ;
 
  void idiv1(void) ;
 
 
 
  void pll4(void) {
 
    CPG.WTCNT = 0x5a00 ;        // Watch dog timer counter = 0
 
    CPG.WTCSR = 0xa502 ;        // 1/16Pclk : 122us ( >100us).
 
    CPG.FRQCR.WORD = 0x0112 ;    // PLL1 is *4 (I:B:P=8:4:2)
 
  }
 
 
 
  void pll3(void) {
 
    CPG.WTCNT = 0x5a00 ;        // Watch dog timer counter = 0
 
    CPG.WTCSR = 0xa502 ;        // 1/16Pclk : 122us ( >100us ). 
 
    CPG.FRQCR.WORD = 0xa101 ;    // PLL1 is *3 (I:B:P=12:4:2)
 
  }
 
 
 
                              // change only CPU clock devider1
 
  void idiv3(void) {
 
    CPG.FRQCR.WORD = 0xe101 ;    // IFC=1/3 (I:B:P=4:4:2)
 
  }
 
 
 
  void idiv1(void);
 
|}
 
  
 
+
void PLL_32x(void) {
For the SH4-A, similar code is used, but with different values; see the above section on the FRQCR layout for more information; one of the main differences between the two's FRQCRs is that the SH3 sports a 16 bit one, and the SH4-A dons a 32 bit one with more ratio control.
+
    unsigned int*FRQCR = (unsigned int*) 0xA4150000;
 +
    *FRQCR = *FRQCR | (0b001111 << 24) & (0b001111 << 24);
 +
    *FRQCR = *FRQCR | (0b1 << 31);
 +
}
 +
  
 
==Precautions when changing clock frequencies==
 
==Precautions when changing clock frequencies==
  
Changing clock frequencies comes with a severe speed penalty. After writing to FRQCR, the CPU will be disabled from operating until register WDT overflows, which typically lasts between 100µs and 200µs. No operations will be performed. This is to allow the clock frequency to stabilize enough for processing to resume. If you choose to change the clock frequency, do not forget to reset WDT with
+
Making the PLL circuit multiplier a non-valid value, will lead to the Prizm crashing.
{
 
  CPG.WTCNT = 0x5a00 ;
 
  CPG.WTCSR = 0xa502 ;
 
}
 
If it is not reset, then the processor may begin to fail to correctly read from RAM, among other things. Similar events are likely to happen if you overclock the frequency beyond its limits, which is 200 MHz.
 
 
 
 
 
==Overclocking==
 
 
 
Cfxm acquired the following information from Simon (documented [http://www.cemetech.net/forum/viewtopic.php?p=173935#173935 here]):
 
 
 
Beim Clock Pulse Generator handelt es sich offensichtlich fast um den des Mutter-Prozessors 7730.
 
Im Bootcode wird Folgendes gemacht:
 
 
 
ROM:800006B6 mov.l @(h'C4,pc), r6 ; [8000077C] = FRQCR
 
ROM:800006B8 mov.l @(h'C4,pc), r7 ; [80000780] = h'F00F0
 
ROM:800006BA mov.l @(h'C8,pc), r1 ; [80000784] = h'8F102203
 
ROM:800006BC mov.l @r6, r2
 
ROM:800006BE and r7, r2
 
ROM:800006C0 or r1, r2
 
ROM:800006C2 mov.l r2, @r6
 
 
 
Die verwenden einige undokumentierte bzw. verbotene Bit-Kombinationen.
 
 
 
HIGH 10 prohibited
 
PLL 01111 x16
 
CPU 0001 prohibited
 
SH 0010 x1/2
 
Bus 0010 x1/2
 
Peripheral 0011 prohibited
 
 
 
Da kann man nur ausprobieren.
 
Ich selbst glaube daran, dass Übertakten, wenn es auch keine sofortigen Konsequenzen hat,
 
die Schaltkreise strapaziert, d. h. die Lebensdauer verringert.
 
Der Prozessor muss definitiv bei einer höheren Temperatur arbeiten.
 
Batterie-Lebensdauer wird auch kürzer sein.
 
 
 
 
 
An idea to execute overclocking code was proposed to be done by copying the code out of Virtual Memory space, and into real space by allocating a chunk of memory on the heap, copying an overclocking function over, and calling it.  This will not work, unfortunately; any code executed from the heap seems to cause an immediate crash and system shut down.
 
  
 
==References==
 
==References==

Revision as of 20:01, 1 April 2012

The SH7724 processor used by the Casio Prizm, a SuperH 4-A with no FPU, utilizes four clocks to regulate commands. These clocks are known as the CPU clock, the data bus clock, the SH clock and the peripheral clock.

CPU clock

The CPU clock is the main clock used by the processor. It directly controls the speed of the processor. The CPU clock itself is controlled by a clock pulse generator (CPG). The CPG consists of a input clock signal from a Crystal oscillator which is divided to achieve the standard 58 MHz clock frequency of the Prizm. The circuit also contains two internal phase locked loops (PLL circuits) which output data about the state of the CPG.

Peripheral clock

The peripheral clock operates similarly to the CPU clock and is derived from the same CPG signal. It's used to operate peripheral modules and also controls several registers with the CPG control unit, such as the FRQCR (Frequency Control Register)

Bus clock

This clock controls the speed of memory reads and other hardware related functions. Its frequency is determined upon boot by the load on the CKIO pin and can take the the value of either 1x or 4x the frequency of the crystal oscillator. This value cannot be changed after startup. The bus clock is also used as the signal source for the Peripheral and CPU clocks. If the set division ratio correlates to a speed over 200Mhz, memory operations may go haywire.

SH clock

This clock, the SuperHyway clock, affects the speed of the SuperHyway bus that connects most operations within the processor, such as instruction fetching/sending, and IL data access.

Registers

There is one register used to modify the CPG. This is the Frequency Control Register (FRQCR), a longword memory-mapped to 0xA4150000, which can only be accessed as a longword for Read and Write operations. A description of it in technical bit-field breakdown is below:

/* 
* FRQCR 
* 31: Kick 
*   Writing 1 here updates CPG settings 
* 29-24: PLL 
*   Multiplier = (PLL + 1) * 2 
* 23-20: I_CLK 
*   CPU Clock Divisor 
* 15-12: SH_CLK 
*   SuperHighway Clock Divisor 
* 11-8: B_CLK 
*   Bus Clock Divisor 
* 3-0: P_CLK 
*   Peripheral Clock Divisor 
* 
* Divisor values: 
*   0000 x1/2 
*   0001 x1/3 
*   0010 x1/4 
*   0011 x1/6 
*   0100 x1/8 
*   0101 x1/12 
*   0110 x1/16 
*   1000 x1/24 
*   1001 x1/32 
*   1010 x1/36 
*   1011 x1/48 
*   1101 x1/72 
* 
* Updates to the FRQCR do not go into effect until 1 is written to the kick bit. 
*--------------------------------------------------------------------------------- 
* 
* Before using the watchdog timer it migt be necessary to call enable_mtspcr(0, 13), 
* this will enable the RCLK signal to the WDT. 
*/ 

Changing clock frequencies

The one circuit that needs to be changed to make a difference in clock speed is the PLL circuit. The Prizm runs at 32x frequency, which is 58MHz (the base frequency is ~1.8MHz). It can be overclocked to at most 87MHz. One can simply write a new longword with the new PLL multiplication value to the FRQCR, and then rewrite it again with the top bit [31] (the FRQCR Kick, which needs to be set to 1 to "kick" the new value into place) set to change the frequencies. Valid PLL multiplication ratios are:

0b000101:×12 
0b000111:×16 
0b001011:×24 
0b001110:×30 
0b001111:×32 
0b010001:×36 
0b010111:×48 

Example code

The below will overclock the PLL circuit to 48x, effectively changing the frequency to 87MHz.

void PLL_48x(void) {
   unsigned int*FRQCR = (unsigned int*) 0xA4150000;
   *FRQCR = *FRQCR | (0b010111 << 24) & (0b010111 << 24);
   *FRQCR = *FRQCR | (0b1 << 31);
}

To reset the frequency to normal speed:

void PLL_32x(void) {
   unsigned int*FRQCR = (unsigned int*) 0xA4150000;
   *FRQCR = *FRQCR | (0b001111 << 24) & (0b001111 << 24);
   *FRQCR = *FRQCR | (0b1 << 31);
}

Precautions when changing clock frequencies

Making the PLL circuit multiplier a non-valid value, will lead to the Prizm crashing.

References

<references/>