CPU Clocks

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The SuperH 3 processor used by the Casio Prizm utilizes three clocks to regulate commands. These clocks are known as the CPU clock, the data bus clock, and the peripheral clock.

CPU clock

The CPU clock is the main clock used by the processor. It directly controls the speed of the processor. The CPU clock itself is controlled by a clock pulse generator (CPG).<ref>http://resource.renesas.com/lib/eng/e_learnig/sh4/40/index.html</ref> The CPG consists of a input clock signal from a Crystal oscillator which is divided to achieve the standard 29 MHz clock frequency of the Prizm. The circuit also contains two internal phase locked loops (PLL circuits) which output data about the state of the CPG.

Peripheral clock

The peripheral clock operates similarly to the CPU clock and is derived from the same CPG signal. It's used to operate peripheral modules and also controls several registers with the CPG control unit.

Bus clock

This clock controls the speed of memory reads and other hardware related functions. Its frequency is determined upon boot by the load on the CKIO pin and can take the the value of either 1x or 4x the frequency of the crystal oscillator. This value cannot be changed after startup. The bus clock is also used as the signal source for the Peripheral and CPU clocks.


There are four registers used to modify the CPG. These are the Frequency Control Register (FRQCR), the WatchDog timer Control Register (WDTCR), and Standby Control Registers 1 and 2 (STBCR & STBCR2).

Changing clock frequencies

One feature of the SuperH 3 processor is its ability to change operating speed. This is accomplished by writing data to the FRQCR. The FRQCR is a two byte register within the CPG control unit responsible for multiplying the frequency of the base clock signal and controlling the frequency ratios of the CPU and peripheral clocks. Each of these attributes is given three bits within the register.<ref>http://resource.renesas.com/lib/eng/e_learnig/superh_e_learning/36/index.html</ref>

FRQCR register
Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
STC2 IFC2 PFC2 ---- ---- ---- ---- ---- ---- ---- STC1 STC0 IFC1 IFC0 PFC1 PFC0
Permissions R/W R/W R/W R R R R R R R R/W R/W R/W R/W R/W R/W

Frequency multiplier
STC2 STC1 STC0 Factor
0 0 0 x1
0 0 1 x2
1 0 0 x3
0 1 0 x4

CPU clock frequency ratio
IFC2 IFC1 IFC0 Factor
0 0 0 x1
0 0 1 x1/2
1 0 0 x1/3
0 1 0 x1/4

Peripheral clock ratio
PFC2 PFC1 PFC0 Factor
0 0 0 x1
0 0 1 x1/2
1 0 0 x1/3
0 1 0 x1/4
1 0 1 x1/6

Example code

According to a manufacturer of the SH3 processor, Renesas, clock frequencies can be changed with the following C code:<ref>http://resource.renesas.com/lib/eng/e_learnig/superh_e_learning/38/list.html</ref>

Changing clock frequencies

/* Clock Pulse Generater sample program

 Mode = 2
 X'tal = 16.7MHz
 PLL1 = *4
 FRQCR H'0102(startup)
  • /
  1. include "iodefine.h"

void pll4(void) ; void pll3(void) ; void idiv3(void) ; void idiv1(void) ;

void pll4(void) {

 CPG.WTCNT = 0x5a00 ;         // Watch dog timer counter = 0
 CPG.WTCSR = 0xa502 ;         // 1/16Pclk : 122us ( >100us)
 CPG.FRQCR.WORD = 0x0112 ;    // PLL1 is *4 (I:B:P=8:4:2)


void pll3(void) {

 CPG.WTCNT = 0x5a00 ;         // Watch dog timer counter = 0
 CPG.WTCSR = 0xa502 ;         // 1/16Pclk : 122us ( >100us )
 CPG.FRQCR.WORD = 0xa101 ;    // PLL1 is *3 (I:B:P=12:4:2)


                              // change only CPU clock devider1

void idiv3(void) {

 CPG.FRQCR.WORD = 0xe101 ;    // IFC=1/3 (I:B:P=4:4:2)


void idiv1(void)

Precautions when changing clock frequencies

Changing clock frequencies comes with a severe speed penalty. After writing to FRQCR, the CPU will be disabled from operating until register WDT overflows, which typically lasts between 100µs and 200µs. No operations will be performed. This is to allow the clock frequency to stabilize enough for processing to resume. If you choose to change the clock frequency, do not forget to reset WDT with

 CPG.WTCNT = 0x5a00 ;
 CPG.WTCSR = 0xa502 ;

If it is not reset, then the processor may begin to fail to correctly read from RAM, among other things. Similar events are likely to happen if you overclock the frequency beyond its limits, which is 200 MHz.


Cfxm acquired the following information from Simon (documented here):

Beim Clock Pulse Generator handelt es sich offensichtlich fast um den des Mutter-Prozessors 7730.
Im Bootcode wird Folgendes gemacht:
ROM:800006B6 mov.l @(h'C4,pc), r6 ; [8000077C] = FRQCR
ROM:800006B8 mov.l @(h'C4,pc), r7 ; [80000780] = h'F00F0
ROM:800006BA mov.l @(h'C8,pc), r1 ; [80000784] = h'8F102203
ROM:800006BC mov.l @r6, r2
ROM:800006BE and r7, r2
ROM:800006C0 or r1, r2
ROM:800006C2 mov.l r2, @r6
Die verwenden einige undokumentierte bzw. verbotene Bit-Kombinationen.
HIGH 10 prohibited
PLL 01111 x16
CPU 0001 prohibited
SH 0010 x1/2
Bus 0010 x1/2
Peripheral 0011 prohibited
Da kann man nur ausprobieren.
Ich selbst glaube daran, dass Übertakten, wenn es auch keine sofortigen Konsequenzen hat,
die Schaltkreise strapaziert, d. h. die Lebensdauer verringert.
Der Prozessor muss definitiv bei einer höheren Temperatur arbeiten.
Batterie-Lebensdauer wird auch kürzer sein.