Difference between revisions of "Peripherals"

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m (Added CMT and PFC as well as some unknowns.)
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|A400 001C||4||{{yes}}||{{yes}}||Writes 0x800 on cold start
 
|A400 001C||4||{{yes}}||{{yes}}||Writes 0x800 on cold start
 
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|A400 0024||4||{yes}}||{{no}}||
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|A400 0024||4||{{yes}}||{{no}}||
 
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|A42F 0004||4||{{no}}||{{yes}}||Right after reading BSC, before reading/write to A400001C
 
|A42F 0004||4||{{no}}||{{yes}}||Right after reading BSC, before reading/write to A400001C
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|A405 018A||2||{{no}}||{{yes}}||Writes 0x5515 on cold start. Overlaps with the SH7724's PFC
 
|A405 018A||2||{{no}}||{{yes}}||Writes 0x5515 on cold start. Overlaps with the SH7724's PFC
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|A408 0008||2||{{yes}}||{{yes}}||Reads and writes 0 back.
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|A408 008C||1||{{no}}||{{yes}}||Writes 0xC
 
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|FEC1 5040||2||{{yes}}||{{no}}||Reads on boot in a BSC-reading block.  If this is the SH7730, then it read 2 bytes in a write-only 4-byte SDRAM mode register.
 
|FEC1 5040||2||{{yes}}||{{no}}||Reads on boot in a BSC-reading block.  If this is the SH7730, then it read 2 bytes in a write-only 4-byte SDRAM mode register.

Revision as of 21:29, 10 February 2015

The SH7305 is comprised of many different peripherals that surround a SH4a core in the SH7305. Due to a lack of known documentation, the peripherals included in the SH7305 are guessed based on similarities to other SuperH CPUs with known documentation.

Unknown Peripherals

Please document all reads/writes to unknown peripherals. This is an effort to produce documentation by analyzing their usage. Please report the address, access size in bytes, mark read and/or write, and note what the surrounding code was doing or any hypothesis about the function. Note that 0x8xxxxxxx-0x9xxxxxxx and 0xAxxxxxxx-0xBxxxxxxx addresses are identical, standardize on 0xAxxxxxxx-0xBxxxxxxx addresses.

Address Size Read Write Notes
A400 0010 4 No Yes Writes 4 on cold start. Later, reads it, then writes 0x808 and 0.
A400 001C 4 Yes Yes Writes 0x800 on cold start
A400 0024 4 Yes No
A42F 0004 4 No Yes Right after reading BSC, before reading/write to A400001C
A405 0184 2 No Yes Writes 0x9554 on cold start. Order for next 3: ...86, ...88, ...8A, ...84. This overlaps with the SH7724's PFC's PULCR (pullup control register), but most likely not the same.
A405 0186 2 No Yes Writes 0x5555 on cold start. Overlaps with the SH7724's PFC
A405 0188 2 No Yes Writes 0x5555 on cold start. Overlaps with the SH7724's PFC
A405 018A 2 No Yes Writes 0x5515 on cold start. Overlaps with the SH7724's PFC
A408 0008 2 Yes Yes Reads and writes 0 back.
A408 008C 1 No Yes Writes 0xC
FEC1 5040 2 Yes No Reads on boot in a BSC-reading block. If this is the SH7730, then it read 2 bytes in a write-only 4-byte SDRAM mode register.

Peripherals List

List of peripherals that match documentation

Name SH Core Base Address Verified Emulated Notes
BSC SH7730 FEC1 0000 No No Assumed to be SH7724 before, register accesses match up with SH7730, maybe others. See FEC1 5040 in table above, oddity.
RTC SH7720 A413 FEC0 Yes No I've tested this, from Simon's docs
RWDT SH7724 A452 0000 No No Matches the documentation
CPG SH7724 A415 0000 Yes Partial It is mostly understood, but there are still hardware quirks that make using this "tricky".
CMT SH7724
SH7730
A44A 0000 Yes No There are OS syscalls for interfacing with the CMT.
PFC Unknown A405 0100 No No See above table for unknown accesses in the PFC.

Peripherals on Cold Start

  • (SH7724) STBCR <- 0 (Standby control)
  • (SH7724) MSTPCR0 <- 0 (module stop 0)
  • (SH7724) MSTPCR0 <- 0xFFFFFFFF (module stop 2)
  • <snip>
  • Watchdog timer is disabled, counter set to 0, and sets the WDT clock to Rφ/64, or 500ms
  • Busy-loop waiting for the R64CNT register to hit != 0. (Verify it wants != 0)

(TODO)