From WikiPrizm
Revision as of 05:15, 10 February 2015 by Ahelper (talk | contribs) (Added a peripherals list as I go through adding in emulation support)
Jump to navigationJump to search

The SH7305 is comprised of many different peripherals that surround a SH4a core in the SH7305. Due to a lack of known documentation, the peripherals included in the SH7305 are guessed based on similarities to other SuperH CPUs with known documentation.

Unknown Peripherals

Please document all reads/writes to unknown peripherals. This is an effort to produce documentation by analyzing their usage. Please report the address, access size in bytes, mark read and/or write, and note what the surrounding code was doing or any hypothesis about the function. Note that 0x8xxxxxxx-0x9xxxxxxx and 0xAxxxxxxx-0xBxxxxxxx addresses are identical, standardize on 0xAxxxxxxx-0xBxxxxxxx addresses.

Address Size Read Write Notes
A405 0184 2 No Yes Writes 0x9554 on cold start. Order for next 3: ...86, ...88, ...8A, ...84. This overlaps with the SH7724's PFC's PULCR (pullup control register), but most likely not the same.
A405 0186 2 No Yes Writes 0x5555 on cold start. Overlaps with the SH7724's PFC
A405 0188 2 No Yes Writes 0x5555 on cold start. Overlaps with the SH7724's PFC
A405 018A 2 No Yes Writes 0x5515 on cold start. Overlaps with the SH7724's PFC

Peripherals List

List of peripherals that match documentation

Name|SH Core|Base Address|Functionality Tested|Notes
SH7730|0xFEC10000|style="background:#F99;vertical-align:middle;text-align:center;" class="table-no"|No|Assumed to be SH7724 before, register accesses match up with SH7730, maybe others

Peripherals on Cold Start

  • (SH7724) STBCR <- 0 (Standby control)
  • (SH7724) MSTPCR0 <- 0 (module stop 0)
  • (SH7724) MSTPCR0 <- 0xFFFFFFFF (module stop 2)